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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
TABLE 18-6: REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE  
Reset  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Values  
on Page:  
INTCON  
GIE/GIEH PEIE/GIEL  
TMR0IE  
INT0IE  
PTIP  
PTIE  
PTIF  
RBIE  
TMR0IF  
IC2QEIP  
IC2QEIE  
IC2QEIF  
INT0IF  
IC1IP  
IC1IE  
IC1IF  
RBIF  
54  
56  
56  
56  
58  
58  
58  
58  
58  
58  
58  
58  
IPR3  
IC3DRIP  
IC3DRIE  
IC3DRIF  
TMR5IP  
TMR5IE  
TMR5IF  
PIE3  
PIR3  
PTCON0  
PTCON1  
PTOPS3  
PTEN  
PTOPS2  
PTDIR  
PTOPS1  
PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0  
(1)  
PTMRL  
PTMRH  
PWM Time Base Register (lower 8 bits)  
(1)  
UNUSED  
PWM Time Base Register (upper 4 bits)  
(1)  
(1)  
PTPERL  
PWM Time Base Period Register (lower 8 bits)  
PTPERH  
UNUSED  
PWM Special Event Compare Register (lower 8 bits)  
UNUSED  
PWM Time Base Period Register (upper 4 bits)  
(1)  
(1)  
SEVTCMPL  
SEVTCMPH  
PWM Special Event Compare Register  
(upper 4 bits)  
(2)  
PWMCON0  
PWMCON1  
DTCON  
PWMEN2  
PWMEN1  
PWMEN0 PMOD3  
PMOD2  
PMOD1  
UDIS  
DT1  
PMOD0  
OSYNC  
DT0  
58  
58  
58  
58  
58  
58  
58  
58  
58  
58  
58  
58  
58  
58  
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR  
DTPS1  
BRFEN  
DTPS0  
DT5  
FLTBMOD  
POVD5  
DT4  
DT3  
DT2  
(2)  
(2)  
(2)  
FLTCONFIG  
OVDCOND  
OVDCONS  
FLTBS  
POVD6  
POUT6  
FLTBEN  
FLTCON  
POVD3  
POUT3  
FLTAS  
POVD2  
POUT2  
FLTAMOD FLTAEN  
(2)  
(2)  
(2)  
POVD7  
POVD4  
POUT4  
POVD1  
POUT1  
POVD0  
POUT0  
(2)  
POUT7  
POUT5  
(1)  
PDC0L  
PWM Duty Cycle #0L Register (lower 8 bits)  
UNUSED PWM Duty Cycle #0H Register (upper 6 bits)  
PWM Duty Cycle #1L register (lower 8 bits)  
(1)  
PDC0H  
(1)  
PDC1L  
(1)  
PDC1H  
UNUSED  
PWM Duty Cycle #1H Register (upper 6 bits)  
(1)  
PDC2L  
PWM Duty Cycle #2L Register (lower 8 bits)  
(1)  
PDC2H  
UNUSED  
PWM Duty Cycle #2H Register (upper 6 bits)  
(1,2)  
PDC3L  
PWM Duty Cycle #3L Register (lower 8 bits)  
(1,2)  
PDC3H  
UNUSED  
PWM Duty Cycle #3H Register (upper 6 bits)  
Legend: — = Unimplemented, read as ‘0’. Shaded cells are not used with the power control PWM.  
Note 1: Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to.  
2: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. Reset values shown are for  
PIC18F4331/4431 devices.  
2010 Microchip Technology Inc.  
DS39616D-page 203  
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