PIC18F2331/2431/4331/4431
The PWM Duty Cycle registers may be used in con-
18.10.3 OUTPUT OVERRIDE EXAMPLES
junction with the OVDCOND and OVDCONS registers.
The Duty Cycle registers control the average voltage
across the load and the OVDCOND and OVDCONS
registers control the commutation sequence.
Figure 18-22 shows the waveforms, while Table 18-4
and Table 18-5 show the OVDCOND and OVDCONS
register values used to generate the signals.
Figure 18-21 shows an example of a waveform that
might be generated using the PWM output override
feature. The figure shows a six-step commutation
sequence for a BLDC motor. The motor is driven
through a 3-phase inverter as shown in Figure 18-16.
When the appropriate rotor position is detected, the
PWM outputs are switched to the next commutation
state in the sequence. In this example, the PWM out-
puts are driven to specific logic states. The OVDCOND
and OVDCONS register values used to generate the
signals in Figure 18-21 are given in Table 18-4.
REGISTER 18-6: OVDCOND: OUTPUT OVERRIDE CONTROL REGISTER
R/W-1
POVD7(1)
bit 7
R/W-1
POVD6(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
POVD<7:0>: PWM Output Override bits
1= Output on PWM I/O pin is controlled by the value in the Duty Cycle register and the PWM time base
0= Output on PWM I/O pin is controlled by the value in the corresponding POUT bit
Note 1: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear.
REGISTER 18-7: OVDCONS: OUTPUT STATE REGISTER(1,2)
R/W-0
POUT7(1)
bit 7
R/W-0
POUT6(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
POUT<7:0>: PWM Manual Output bits
1= Output on PWM I/O pin is active when the corresponding PWM output override bit is cleared
0= Output on PWM I/O pin is inactive when the corresponding PWM output override bit is cleared
Note 1: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear.
2: With PWMs configured in Complementary mode, the output of even numbered PWM (PM0,2,4) will be
complementary of the output of odd PWM (PWM1,3,5), irrespective of the POUT bit setting.
DS39616D-page 196
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
