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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
FIGURE 5-2:  
EXTERNAL POWER-ON  
RESET CIRCUIT (FOR  
SLOW VDD POWER-UP)  
5.2  
Master Clear (MCLR)  
The MCLR pin can trigger an external Reset of the  
device by holding the pin low. These devices have a  
noise filter in the MCLR Reset path that detects and  
ignores small pulses.  
VDD  
VDD  
D
The MCLR pin is not driven low by any internal Resets,  
including the Watchdog Timer.  
R
R1  
MCLR  
In PIC18F2331/2431/4331/4431 devices, the MCLR  
input can be disabled with the MCLRE Configuration  
bit. When MCLR is disabled, the pin becomes a digital  
input. For more information, see Section 11.5  
“PORTE, TRISE and LATE Registers”.  
PIC18FXXXX  
C
Note 1: External Power-on Reset circuit is  
required only if the VDD power-up slope is  
too slow. The diode, D, helps discharge  
the capacitor quickly when VDD powers  
down.  
5.3  
Power-on Reset (POR)  
A Power-on Reset pulse is generated on-chip when-  
ever VDD rises above a certain threshold. This allows  
the device to start in the initialized state when VDD is  
adequate for operation.  
2: R < 40 kis recommended to make  
sure that the voltage drop across R does  
not violate the device’s electrical  
specification.  
To take advantage of the POR circuitry, tie the MCLR  
pin through a resistor (1 kto 10 k) to VDD. This will  
eliminate external RC components usually needed to  
create a Power-on Reset delay. The minimum rise rate  
for VDD is specified (Parameter D004). For a slow rise  
time, see Figure 5-2.  
3: R1 1 kwill limit any current flowing  
into MCLR from external capacitor, C, in  
the event of MCLR/VPP pin breakdown,  
due to Electrostatic Discharge (ESD) or  
Electrical Overstress (EOS).  
When the device starts normal operation (i.e., exits the  
Reset condition), device operating parameters (such  
as voltage, frequency and temperature) must be met to  
ensure operation. If these conditions are not met, the  
device must be held in Reset until the operating  
conditions are met.  
5.4  
Brown-out Reset (BOR)  
A Configuration bit, BOREN, can disable (if clear/  
programmed) or enable (if set) the Brown-out Reset  
circuitry. If VDD falls below VBOR (Parameter D005A  
through D005F) for greater than TBOR (Parameter 35),  
the brown-out situation will reset the chip. A Reset may  
not occur if VDD falls below VBOR for less than TBOR.  
The chip will remain in Brown-out Reset until VDD rises  
above VBOR. If the Power-up Timer is enabled, it will be  
invoked after VDD rises above VBOR; it then will keep  
the chip in Reset for an additional time delay TPWRT  
(Parameter 33). If VDD drops below VBOR while the  
Power-up Timer is running, the chip will go back into a  
Brown-out Reset and the Power-up Timer will be  
initialized. Once VDD rises above VBOR, the Power-up  
Timer will execute the additional time delay. Enabling  
the Brown-out Reset does not automatically enable the  
PWRT.  
Power-on Reset events are captured by the POR bit  
(RCON<1>). The state of the bit is set to ‘0’ whenever  
a POR occurs and does not change for any other Reset  
event. POR is not reset to ‘1’ by any hardware event.  
To capture multiple events, the user manually resets  
the bit to ‘1’ in software following any Power-on Reset.  
Note:  
The following decoupling method is  
recommended:  
1. A 1 F capacitor should be connected  
across AVDD and AVSS.  
2. A similar capacitor should be  
connected across VDD and VSS.  
2010 Microchip Technology Inc.  
DS39616D-page 49  
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