PIC17C4X
12.2.1 ONE CAPTURE AND ONE PERIOD
REGISTER MODE
Capture pin RB1/CAP2 is a multiplexed pin.When used
as a port pin, Capture2 is not disabled. However, the
user can simply disable the Capture2 interrupt by clear-
ing CA2IE. If RB1/CAP2 is used as an output pin, the
user can activate a capture by writing to the port pin.
This may be useful during development phase to emu-
late a capture interrupt.
In this mode registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 12-7. The timer increments until it
equals the period register and then resets to 0000h.
TMR3 Interrupt Flag bit (TMR3IF) is set at this point.
This interrupt can be disabled by clearing the TMR3
Interrupt Enable bit (TMR3IE). TMR3IF must be
cleared in software.
The input on capture pin RB1/CAP2 is synchronized
internally to internal phase clocks.This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
This mode is selected if control bit CA1/PR3 is clear. In
this mode, the Capture1 register, consisting of high
byte (PR3H/CA1H) and low byte (PR3L/CA1L), is con-
figured as the period control register for TMR3.
Capture1 is disabled in this mode, and the correspond-
ing Interrupt bit CA1IF is never set. TMR3 increments
until it equals the value in the period register and then
resets to 0000h.
The Capture2 overflow status flag bit is double buff-
ered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the Timer3 value to the capture
register, protecting the previous unread capture value.
When the user reads both the high and the low bytes (in
any order) of the Capture2 register, the master overflow
bit is transferred to the slave overflow bit (CA2OVF) and
then the master bit is reset. The user can then read
TCON2 to determine the value of CA2OVF.
Capture2 is active in this mode. The CA2ED1 and
CA2ED0 bits determine the event on which capture will
occur. The possible events are:
• Capture on every falling edge
• Capture on every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
The recommended sequence to read capture registers
and capture overflow flag bits is shown in
Example 12-1.
EXAMPLE 12-1: SEQUENCE TO READ
CAPTURE REGISTERS
When a capture takes place, an interrupt flag is latched
into the CA2IF bit.This interrupt can be enabled by set-
ting the corresponding mask bit CA2IE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CA2IF interrupt flag
bit must be cleared in software.
MOVLB 3
;Select Bank 3
MOVPF CA2L,LO_BYTE
;Read Capture2 low
;byte, store in LO_BYTE
;Read Capture2 high
;byte, store in HI_BYTE
MOVPF CA2H,HI_BYTE
MOVPF TCON2,STAT_VAL ;Read TCON2 into file
;STAT_VAL
When the capture prescale select is changed, the pres-
caler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip reset.
FIGURE 12-7: TIMER3 WITH ONE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
PR3H/CA1H
PR3L/CA1L
(TCON1<2>)
Set TMR3IF
(PIR<6>)
CCoommppaarraatotor<r8x>16
Equal
Reset
0
Fosc/4
TMR3H
TMR3L
1
TMR3ON
(TCON2<2>)
RB5/TCLK3
RB1/CAP2
Capture1 Enable
CA2H
CA2L
Edge select
prescaler select
Set CA2IF
(PIR<3>)
2
CA2ED1: CA2ED0
(TCON1<7:6>)
DS30412C-page 78
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
