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PIC17LC752-25/P 参数 Datasheet PDF下载

PIC17LC752-25/P图片预览
型号: PIC17LC752-25/P
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS微控制器的EPROM [High-Performance 8-Bit CMOS EPROM Microcontrollers]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 320 页 / 2172 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C75X  
2
FIGURE E-12: I C BUS DATA TIMING SPECIFICATION  
103  
102  
100  
101  
SCL  
90  
106  
107  
91  
92  
SDA  
In  
110  
109  
109  
SDA  
Out  
2
TABLE E-3:  
I C BUS DATA TIMING SPECIFICATION  
Microchip  
Parameter  
No.  
Sym  
Characteristic  
Min  
Max  
Units  
Conditions  
100  
101  
102  
THIGH  
Clock high time  
Clock low time  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
4.0  
0.6  
µs  
µs  
µs  
µs  
ns  
ns  
TLOW  
TR  
4.7  
1.3  
SDA and SCL rise  
time  
1000  
300  
20 + 0.1Cb  
Cb is specified to be from  
10 to 400 pF  
103  
TF  
SDA and SCL fall time 100 kHz mode  
400 kHz mode  
300  
300  
ns  
ns  
20 + 0.1Cb  
Cb is specified to be from  
10 to 400 pF  
90  
91  
TSU:STA START condition  
setup time  
100 kHz mode  
400 kHz mode  
4.7  
0.6  
4.0  
0.6  
0
µs  
µs  
µs  
µs  
ns  
µs  
ns  
ns  
µs  
µs  
ns  
ns  
µs  
µs  
Only relevant for repeated  
START condition  
THD:STA START condition hold 100 kHz mode  
After this period the first clock  
pulse is generated  
time  
400 kHz mode  
100 kHz mode  
400 kHz mode  
106  
107  
92  
THD:DAT Data input hold time  
0
0.9  
TSU:DAT Data input setup time 100 kHz mode  
400 kHz mode  
250  
100  
4.7  
0.6  
Note 2  
TSU:STO STOP condition setup 100 kHz mode  
time  
400 kHz mode  
100 kHz mode  
400 kHz mode  
100 kHz mode  
400 kHz mode  
109  
110  
TAA  
Output valid from  
clock  
3500  
1000  
Note 1  
TBUF  
Bus free time  
4.7  
1.3  
Time the bus must be free  
before a new transmission  
can start  
D102  
Cb  
Bus capacitive loading  
400  
pF  
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of  
the falling edge of SCL to avoid unintended generation of START or STOP conditions.  
2
2
2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement tsu;DAT 250 ns must  
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a  
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line  
2
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is  
released.  
DS30264A-page 272  
Preliminary  
1997 Microchip Technology Inc.  
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