PIC17C75X
FIGURE F-4: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U - 0
—
U - 0
—
R - 1
STKAV GLINTD
R/W - 1
R - 1
TO
R - 1
PD
R/W - 0 R/W - 0
POR BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
bit 4:
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
bit 3:
bit 2:
bit 1:
bit 0:
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDTinstruction
0 = A Watchdog Timer time-out occurred
PD: Power-down Status bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set by software after a Brown-out Reset occurs)
DS30264A-page 276
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
