PIC17C75X
FIGURE 20-18: MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
addr out
154
data out
AD<15:0>
addr out
152
153
TABLE 20-19: MEMORY INTERFACE WRITE REQUIREMENTS
Param.
No.
Sym
TadV2alL AD<15:0> (address) valid to
ALE↓ (address setup time) PIC17LCXXX
Characteristic
Min
Typ†
Max Units Conditions
150
PIC17CXXX
0.25Tcy - 10
—
—
ns
—
TBD
0
—
—
—
151
152
TalL2adI
ALE↓ to address out invalid
PIC17CXXX
—
ns
—
(address hold time)
PIC17LCXXX
TBD
TadV2wrL Data out valid to WR↓
(data setup time)
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
0.25Tcy - 40
—
—
—
ns
—
TBD
—
153
154
TwrH2adI WR↑ to data out invalid
(data hold time)
0.25TCY §
TBD
—
ns
—
—
TwrL
WR pulse width
—
0.25TCY §
TBD
—
ns
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 247
MICROCHIP [ MICROCHIP ]
