PIC17C75X
FIGURE 20-17: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 TCY
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 20-18: A/D CONVERSION REQUIREMENTS
Param.
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
TOSC based, VREF ≥ 3.0V
130
TAD
A/D clock period
PIC17CXXX
PIC17LCXXX
PIC17CXXX
PIC17LCXXX
1.6
3.0
—
—
—
µs
—
µs TOSC based, VREF full range
µs A/D RC Mode
µs A/D RC Mode
TAD
2.0 *
3.0 *
12 §
4.0
6.0
—
6.0 *
9.0 *
13 §
131
132
TCNV Conversion time
(not including acquisition time) (Note 1)
TACQ Acquisition time
(Note 2)
10 *
40
—
—
—
µs
µs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e. 5mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
134
TGO
Q4 to ADCLK start
—
Tosc/2 §
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
sleep instruction to be exe-
cuted.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 16.1 for minimum conditions when input voltage has changed more then 1 LSb.
DS30264A-page 246
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
