PIC17C75X
FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
BIT6 - - - - - -1
MSB
LSB
SDO
SDI
75, 76
MSB IN
74
BIT6 - - - -1
LSB IN
73
Refer to Figure 20-1 for load conditions.
TABLE 20-9: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
70
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY *
—
—
ns
71
72
73
TscH
TscL
SCK input high time (slave mode)
SCK input low time (slave mode)
TCY + 20 *
TCY + 20 *
100 *
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
100 *
—
—
ns
75
76
78
79
80
TdoR
TdoF
TscR
TscF
SDO data output rise time
—
—
—
—
—
10
10
10
10
—
25 *
25 *
25 *
25 *
50 *
ns
ns
ns
ns
ns
SDO data output fall time
SCK output rise time (master mode)
SCK output fall time (master mode)
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
*
Characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are no
tested.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 237
MICROCHIP [ MICROCHIP ]
