PIC17C75X
FIGURE 20-5: TIMER0 EXTERNAL CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 20-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS
Param.
No.
Sym Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width No Prescaler
0.5TCY + 20 §
—
—
ns
With Prescaler
Tt0L T0CKI Low Pulse Width No Prescaler
With Prescaler
10*
0.5TCY + 20 §
10*
—
—
—
—
—
—
—
—
ns
ns
ns
41
42
Tt0P T0CKI Period
Greater of:
ns N = prescale value
(1, 2, 4, ..., 256)
20 ns or Tcy + 40 §
N
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
FIGURE 20-6: TIMER1, TIMER2, AND TIMER3 EXTERNAL CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 20-6: TIMER1, TIMER2, AND TIMER3 EXTERNAL CLOCK REQUIREMENTS
Param.
No.
Typ
†
Sym
Characteristic
Min
Max
Units Conditions
45
46
47
Tt123H TCLK12 and TCLK3 high time
Tt123L TCLK12 and TCLK3 low time
Tt123P TCLK12 and TCLK3 input period
0.5TCY + 20 §
0.5TCY + 20 §
—
—
—
—
—
—
ns
ns
TCY + 40 §
N
ns N = prescale value
(1, 2, 4, 8)
48
TckE2tmrI Delay from selected External Clock Edge to
Timer increment
2TOSC §
—
6Tosc §
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 235