PIC17C75X
TABLE 14-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
17h, Bank 1
13h, Bank 0
16h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
PIR1
RBIF
RBIE
SPEN
TX7
TMR3IF TMR2IF TMR1IF CA2IF
TMR3IE TMR2IE TMR1IE CA2IE
CA1IF
CA1IE
FERR
TX2
TX1IF
TX1IE
OERR
TX1
RC1IF
RC1IE
RX9D
TX0
0000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
0000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
PIE1
RCSTA1
TXREG1
TXSTA1
SPBRG1
PIR2
RX9
TX6
TX9
SREN
TX5
CREN
TX4
—
TX3
—
CSRC
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
SSPIF
SSPIE
SPEN
TX7
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
TX5
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
FERR
TX2
TX2IF
TX2IE
OERR
TX1
RC2IF
RC2IE
RX9D
TX0
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
TX4
TX6
TX3
—
CSRC
TX9
TXEN
SYNC
—
TRMT
TX9D
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for synchronous
master transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
FIGURE 14-9: SYNCHRONOUS TRANSMISSION
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit1
bit2
bit0
DT
(RX/DT pin)
bit0
bit7
Word 1
Word 2
CK
(TX/CK pin)
Write to
TXREG
Write word 2
Write word 1
TXIF
Interrupt flag
TRMT
'1'
TXEN
FIGURE 14-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT
bit0
bit2
bit1
bit6
bit7
(RX/DT pin)
CK
(TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
DS30264A-page 118
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
