PIC17C75X
FIGURE 14-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
TX
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8
(TX/CK pin)
Stop Bit
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
FIGURE 14-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
Start Bit
Start Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
(TX/CK pin)
Word 1
TXIF bit
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
Note: This timing diagram shows two consecutive transmissions.
TABLE 14-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
17h, Bank 1
13h, Bank 0
16h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
16h, Bank 4
15h, Bank 4
17h, Bank 4
PIR1
RBIF
RBIE
SPEN
TMR3IF TMR2IF TMR1IF CA2IF CA1IF
TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX1IF
TX1IE
OERR
RC1IF
RC1IE
RX9D
0000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
xxxx xxxx
0000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
uuuu uuuu
PIE1
RCSTA1
TXREG1
TXSTA1
SPBRG1
PIR2
RX9
SREN
CREN
—
FERR
Serial port transmit register (USART1)
CSRC TX9 TXEN SYNC
Baud rate generator register (USART1)
—
—
TRMT
TX9D
SSPIF
SSPIE
SPEN
BCLIF
BCLIE
RX9
ADIF
ADIE
SREN
—
—
CA4IF CA3IF
CA4IE CA3IE
TX2IF
TX2IE
OERR
RC2IF
RC2IE
RX9D
PIE2
RCSTA2
TXREG2
TXSTA2
SPBRG2
CREN
—
FERR
Serial port transmit register (USART2)
CSRC TX9 TXEN SYNC
Baud rate generator register (USART2)
—
—
TRMT
TX9D
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30264A-page 114
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
