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PIC17C752T-25I/P 参数 Datasheet PDF下载

PIC17C752T-25I/P图片预览
型号: PIC17C752T-25I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS微控制器的EPROM [High-Performance 8-Bit CMOS EPROM Microcontrollers]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 320 页 / 2172 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C75X  
13.2.4 EXTERNAL CLOCK INPUT FOR TIMER3  
13.2.5 READING/WRITING TIMER3  
When TMR3CS is set, the 16-bit TMR3 increments on  
the falling edge of clock input TCLK3. The input on the  
RB5/TCLK3 pin is sampled and synchronized by the  
internal phase clocks twice every instruction cycle.This  
causes a delay from the time a falling edge appears on  
TCLK3 to the time TMR3 is actually incremented. For  
the external clock input timing requirements, see the  
Electrical Specification section. Figure 13-10 shows  
the timing diagram when operating from an external  
clock.  
Since Timer3 is a 16-bit timer and only 8-bits at a time  
can be read or written, care should be taken when  
reading or writing while the timer is running. The best  
method is to stop the timer, perform any read or write  
operation, and then restart Timer3 (using the TMR3ON  
bit). However, if it is necessary to keep Timer3 free-run-  
ning, care must be taken. For writing to the 16-bit  
TMR3, Example 13-2 may be used. For reading the  
16-bit TMR3, Example 13-3 may be used. Interrupts  
must be disabled during this routine.  
EXAMPLE 13-2: WRITING TO TMR3  
BSF  
CPUSTA, GLINTD  
RAM_L, TMR3L  
RAM_H, TMR3H  
CPUSTA, GLINTD  
; Disable interrupts  
;
;
MOVFP  
MOVFP  
BCF  
; Done, enable interrupts  
EXAMPLE 13-3: READING FROM TMR3  
MOVPF  
MOVPF  
MOVFP  
CPFSLT TMR3L, WREG  
RETURN  
MOVPF  
MOVPF  
RETURN  
TMR3L, TMPLO  
TMR3H, TMPHI  
TMPLO, WREG  
; read low TMR3  
; read high TMR3  
; tmplo −> wreg  
; TMR3L < wreg?  
; no then return  
; read low TMR3  
; read high TMR3  
; return  
TMR3L, TMPLO  
TMR3H, TMPHI  
FIGURE 13-10: TIMER1, TIMER2, AND TIMER3 OPERATION (IN COUNTER MODE)  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
TCLK12  
or TCLK3  
34h  
35h  
A8h  
A9h  
00h  
TMR1, TMR2, or TMR3  
PR1, PR2, or PR3H:PR3L  
WR_TMR  
'A9h'  
'A9h'  
RD_TMR  
TMRxIF  
MOVWF  
TMRx  
MOVFP  
MOVFP  
TMRx,W  
TMRx,W  
Instruction  
executed  
Write to TMRx  
Read TMRx  
Read TMRx  
Note 1: TCLK12 is sampled in Q2 and Q4.  
2: ↓ indicates a sampling point.  
3: The latency from TCLK12 to timer increment is between 2Tosc and 6Tosc.  
DS30264A-page 104  
Preliminary  
1997 Microchip Technology Inc.  
 
 
 
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