PIC16F913/914/916/917/946
FIGURE 13-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
EEADRH,EEADRL
P C + 3
PC+3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
BSF EECON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 1)
executed here
Forced NOP
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
register
EERHLT
TABLE 13-1: SUMMARY OF ASSOCIATED REGISTERS WITH DATA EEPROM
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE1
GIE
EEIE
EEIF
—
PEIE
ADIE
ADIF
—
T0IE
RCIE
RCIF
—
INTE
TXIE
TXIF
RBIE
SSPIE
SSPIF
T0IF
INTF
RBIF
0000 000x
0000 0000
0000 0000
---0 0000
0000 0000
0--- x000
---- ----
--00 0000
0000 0000
0000 000x
0000 0000
0000 0000
---0 0000
0000 0000
---- q000
--------
--00 0000
0000 0000
CCP1IE
CCP1IF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
PIR1
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
EEADRH
EEADRL
EECON1
EECON2
EEDATH
EEDATL
Legend:
EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0
EEPGD WRERR WREN WR RD
EEPROM Control Register 2 (not a physical register)
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
—
—
—
—
—
EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0
x= unknown, u= unchanged, -= unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by data EEPROM module.
DS41250F-page 192
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
