PIC16C71X
4.2
Data Memory Organization
FIGURE 4-4: PIC16C710/71 REGISTER FILE
MAP
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
File
Address
File
Address
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
TMR0
PCL
OPTION
PCL
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
(2)
PCON
ADCON0
ADRES
ADCON1
ADRES
4.2.1
GENERAL PURPOSE REGISTER FILE
PCLATH
INTCON
PCLATH
INTCON
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
General
Purpose
Register
General
Purpose
Register
Mapped
(3)
in Bank 0
AFh
B0h
2Fh
30h
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
2: The PCON register is not implemented on the
PIC16C71.
3: These locations are unimplemented in Bank 1.
Any access to these locations will access the
corresponding Bank 0 register.
DS30272A-page 12
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
