PIC16F716
FIGURE 3-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data Latch
DATA
BUS
Q
D
RA4/T0CKI
WR
PORT
CK
Q
N
TRIS Latch
VSS
Q
D
VSS
WR
TRIS
Schmitt
Trigger
Input
CK
Q
Buffer
RD TRIS
Q
D
EN
EN
RD PORT
Timer0 Clock Input
TABLE 3-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Value on
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
TRISA
—
—
—
—
—
—
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000 ---u uuuu
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
ADCON1
—
—
Legend: x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
DS41206B-page 20
© 2007 Microchip Technology Inc.