PIC16F/LF1946/47
FIGURE 24-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCxIF bit
(Interrupt)
Read
RCxREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 24-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON
BAUD2CON
INTCON
PIE1
ABDOVF
RCIDL
RCIDL
PEIE
ADIE
—
—
SCKP
SCKP
INTE
BRG16
BRG16
IOCIE
SSP1IE
—
—
—
WUE
WUE
ABDEN
ABDEN
IOCIF
300
300
89
ABDOVF
—
GIE
—
TMR0IE
RC1IE
RC2IE
RC1IF
RC2IF
TMR0IF
CCP1IE
—
INTF
TX1IE
TX2IE
TX1IF
TX2IF
TMR2IE
BCL2IE
TMR2IF
BCL2IF
TMR1IE
SSP2IE
TMR1IF
SSP2IF
90
PIE4
—
93
PIR1
—
ADIF
—
SSP1IF
—
CCP1IF
—
94
PIR4
—
93
RC1REG
RC1STA
RC2REG
RC2STA
SP1BRGL
SP1BRGH
SP2BRGL
SP2BRGH
TX1STA
TX2STA
EUSART1 Receive Register
CREN ADDEN
EUSART2 Receive Register
CREN ADDEN
294*
299
294*
299
301*
301*
301*
301*
298
298
SPEN
SPEN
RX9
RX9
SREN
FERR
OERR
OERR
RX9D
RX9D
SREN
FERR
EUSART1 Baud Rate Generator, Low Byte
EUSART1 Baud Rate Generator, High Byte
EUSART2 Baud Rate Generator, Low Byte
EUSART2 Baud Rate Generator, High Byte
CSRC
CSRC
TX9
TX9
TXEN
TXEN
SYNC
SYNC
SENDB
SENDB
BRGH
BRGH
TRMT
TRMT
TX9D
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
Page provides register information.
*
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 313
MICROCHIP [ MICROCHIP ]
