PIC16F/LF1946/47
REGISTER 23-2: SSPxCON1: SSPx CONTROL REGISTER 1
R/C/HS-0/0
WCOL
R/C/HS-0/0
SSPxOV
R/W-0/0
SSPxEN
R/W-0/0
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware C = User cleared
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0= No collision
Slave mode:
1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0= No collision
bit 6
SSPxOV: Receive Overflow Indicator bit(1)
In SPI mode:
1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode
(must be cleared in software).
0= No overflow
bit 5
SSPxEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3)
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCLx release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPxM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4)
1001= Reserved
1010= SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDAx and SCLx pins must be configured as inputs.
SSPxADD values of 0, 1 or 2 are not supported for I2C Mode.
2:
3:
4:
DS41414A-page 284
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
