PIC16F/LF1946/47
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSPx is
being operated in.
23.7 BAUD RATE GENERATOR
The MSSPx module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 23-6).
When a write occurs to SSPxBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Table 23-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 23-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
FOSC
FCLOCK = -------------------------------------------------
SSPxADD + 14
An internal signal “Reload” in Figure 23-39 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 23-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPxM<3:0>
SSPxADD<7:0>
SSPxM<3:0>
SCLx
Reload
Control
Reload
BRG Down Counter
SSPxCLK
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 23-4: MSSPx CLOCK RATE W/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
13h
19h
4Fh
09h
0Ch
27h
09h
400 kHz(1)
308 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS41414A-page 282
Preliminary
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