PIC16F/LF1946/47
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to 0. After the BRG times out, SDAx is
sampled. If SDAx is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 23-37). If the SCLx pin is
sampled low before SDAx is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 23-38).
23.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
b) After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
FIGURE 23-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDAx sampled
low after TBRG,
set BCLxIF
TBRG
TBRG
TBRG
SDAx
SDAx asserted low
SCLx
PEN
BCLxIF
P
’0’
’0’
SSPxIF
FIGURE 23-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDAx
SCLx goes low before SDAx goes high,
set BCLxIF
Assert SDAx
SCLx
PEN
BCLxIF
P
’0’
’0’
SSPxIF
DS41414A-page 280
Preliminary
2010 Microchip Technology Inc.
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