PIC16F/LF1946/47
21.1 Timer2/4/6 Operation
21.3 Timer2/4/6 Output
The clock input to the Timer2/4/6 modules is the
system instruction clock (FOSC/4).
The unscaled output of TMRx is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
TMRx increments from 00h on each clock edge.
Timer2 can be optionally used as the shift clock source
for the MSSPx modules operating in SPI mode.
Additional information is provided in Section 23.0
“Master Synchronous Serial Port (MSSP1 and
MSSP2) Module”.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
TxCKPS<1:0> of the TxCON register. The value of
TMRx is compared to that of the Period register, PRx, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMRx to 00h
on the next cycle and drives the output
counter/postscaler (see Section 21.2 “Timer2/4/6
Interrupt”).
21.4 Timer2/4/6 Operation During Sleep
The Timer2/4/6 timers cannot be operated while the
processor is in Sleep mode. The contents of the TMRx
and PRx registers will remain unchanged while the
processor is in Sleep mode.
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMRx is not cleared when TxCON is written.
21.2 Timer2/4/6 Interrupt
Timer2/4/6 can also generate an optional device
interrupt. The Timer2/4/6 output signal (TMRx-to-PRx
match)
provides
the
input
for
the
4-bit
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMRx Match Interrupt Enable bit, TMRxIE of the PIEx
register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.
DS41414A-page 204
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
