PIC16F/LF1946/47
REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0/0
SRSPE
R/W-0/0
R/W-0/0
SRSC2E
R/W-0/0
SRSC1E
R/W-0/0
SRRPE
R/W-0/0
R/W-0/0
R/W-0/0
SRSCKE
SRRCKE
SRRC2E
SRRC1E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRSPE: SR Latch Peripheral Set Enable bit
1= SR Latch is set when the SRI pin is high
0= SRI pin has no effect on the set input of the SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1= Set input of SR Latch is pulsed with SRCLK
0= SRCLK has no effect on the set input of the SR Latch
SRSC2E: SR Latch C2 Set Enable bit
1= SR Latch is set when the C2 Comparator output is high
0= C2 Comparator output has no effect on the set input of the SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1= SR Latch is set when the C1 Comparator output is high
0= C1 Comparator output has no effect on the set input of the SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1= SR Latch is reset when the SRI pin is high
0= SRI pin has no effect on the reset input of the SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1= Reset input of SR Latch is pulsed with SRCLK
0= SRCLK has no effect on the reset input of the SR Latch
SRRC2E: SR Latch C2 Reset Enable bit
1= SR Latch is reset when the C2 Comparator output is high
0= C2 Comparator output has no effect on the reset input of the SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1= SR Latch is reset when the C1 Comparator output is high
0= C1 Comparator output has no effect on the reset input of the SR Latch
DS41414A-page 184
Preliminary
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
