PIC16F/LF1946/47
TABLE 18-1: SRCLK FREQUENCY TABLE
SRCLK
Divider
FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz
FOSC = 1 MHz
111
110
101
100
011
010
001
000
512
256
128
64
32
16
8
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
39.0 kHz
78.1 kHz
156 kHz
313 kHz
625 kHz
1.25 MHz
2.5 MHz
5 MHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
7.81 kHz
15.6 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
1.95 kHz
3.90 kHz
7.81 kHz
15.6 kHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
2 MHz
4 MHz
2 MHz
4
8 MHz
4 MHz
REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0
SRLEN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SRQEN
R/W-0/0
R/S-0/0
SRPS
R/S-0/0
SRPR
bit 0
SRCLK<2:0>
SRNQEN
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only
bit 7
SRLEN: SR Latch Enable bit
1= SR Latch is enabled
0= SR Latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
bit 6-4
000= Generates a 1 FOSC wide pulse every 4th FOSC cycle clock
001= Generates a 1 FOSC wide pulse every 8th FOSC cycle clock
010= Generates a 1 FOSC wide pulse every 16th FOSC cycle clock
011= Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock
100= Generates a 1 FOSC wide pulse every 64th FOSC cycle clock
101= Generates a 1 FOSC wide pulse every 128th FOSC cycle clock
110= Generates a 1 FOSC wide pulse every 256th FOSC cycle clock
111= Generates a 1 FOSC wide pulse every 512th FOSC cycle clock
bit 3
bit 2
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1= Q is present on the SRQ pin
0= External Q output is disabled
If SRLEN = 0:
SR Latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1= Q is present on the SRnQ pin
0= External Q output is disabled
If SRLEN = 0:
SR Latch is disabled
bit 1
bit 0
SRPS: Pulse Set Input of the SR Latch bit(1)
1= Pulse set input for 1 Q-clock period
0= No effect on set input
SRPR: Pulse Reset Input of the SR Latch bit(1)
1= Pulse reset input for 1 Q-clock period
0= No effect on reset input
Note 1: Set only, always reads back ‘0’.
2010 Microchip Technology Inc.
Preliminary
DS41414A-page 183
MICROCHIP [ MICROCHIP ]
