PIC16C63A/65B/73B/74B
FIGURE 16-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note:
Refer to Figure 16-4 for load conditions.
FIGURE 16-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param No. Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
—
—
µs VDD = 5V, -40°C to +125°C
ms VDD = 5V, -40°C to +125°C
Watchdog Timer Time-out
Period (No Prescaler)
31*
TWDT
TOST
7
18
33
Oscillation Start-up Timer
Period
32
33*
34
—
28
—
1024 TOSC
—
132
2.1
—
—
TOSC = OSC1 period
TPWRT Power-up Timer Period
72
—
—
ms VDD = 5V, -40°C to +125°C
µs
I/O Hi-impedance from MCLR
Low or WDT Reset
TIOZ
35
TBOR Brown-out Reset Pulse Width 100
µs VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
DS30605C-page 126
2000 Microchip Technology Inc.