PIC12F683
4.2.4.6
GP5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-6:
BLOCK DIAGRAM OF GP5
INTOSC
Mode
TMR1LPEN(1)
VDD
Data
Bus
D
Q
Q
WR
WPU
CK
Weak
GPPU
RD
WPU
Oscillator
Circuit
OSC2
VDD
D
Q
Q
WR
GPIO
CK
I/O pin
D
Q
Q
WR
TRISIO
CK
VSS
INTOSC
Mode
RD
TRISIO
(1)
RD
GPIO
D
Q
Q
Q
Q
D
CK
WR
IOC
EN
Q3
RD
IOC
D
EN
Interrupt-on-
change
RD GPIO
To TMR1 or CLKGEN
Note 1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 37
MICROCHIP [ MICROCHIP ]
