PIC12F683
4.2.4.2
GP1/AN1/CIN-/VREF/ICSPCLK
4.2.4.3
GP2/AN2/T0CKI/INT/COUT/CCP1
Figure 4-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
Figure 4-3 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog input for the A/D
• an analog input for the A/D
• the clock input for TMR0
• a analog input to the comparator
• a voltage reference input for the A/D
• In-Circuit Serial Programming clock
• an external edge triggered interrupt
• a digital output from the comparator
• a digital input/output for the CCP (refer to
Section 11.0 “Capture/Compare/PWM (CCP)
Module”).
FIGURE 4-2:
BLOCK DIAGRAM OF GP1
Analog
Data
Input Mode(1)
Bus
FIGURE 4-3:
BLOCK DIAGRAM OF GP2
D
Q
Q
VDD
WR
WPU
CK
Analog
Input Mode
Weak
Data
Bus
D
Q
Q
VDD
GPPU
RD
WR
WPU
CK
WPU
Weak
GPPU
Analog
RD
WPU
VDD
D
Q
Q
COUT
Input
WR
GPIO
CK
Enable
Mode
VDD
D
Q
Q
I/O pin
WR
GPIO
D
Q
Q
CK
COUT
1
0
WR
CK
VSS
Analog
TRISIO
I/O pin
D
Q
Q
Input Mode(1)
RD
WR
TRISIO
TRISIO
CK
VSS
Analog
Input Mode
RD
GPIO
RD
TRISIO
D
Q
Q
Q
Q
D
CK
WR
IOC
RD
GPIO
EN
Q3
D
Q
Q
RD
IOC
Q
Q
D
WR
IOC
D
CK
EN
Q3
EN
Interrupt-on-
change
RD
IOC
D
RD GPIO
EN
Interrupt-on-
change
To Comparator
To A/D Converter
RD GPIO
Note 1: Comparator mode and ANSEL determines Analog
To TMR0
Input mode.
To INT
To A/D Converter
Note 1: Comparator mode and ANSEL determines Analog
Input mode.
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 35
MICROCHIP [ MICROCHIP ]
