PIC12F683
5.4.1
SWITCHING PRESCALER
ASSIGNMENT
5.3
Using Timer0 with an External
Clock
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device Reset, the
following instruction sequence (Example 5-1 and
Example 5-2) must be executed when changing the
prescaler assignment from Timer0 to WDT.
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0 → WDT)
BCF
CLRWDT
CLRF
STATUS,RP0
;Bank 0
Note:
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
TMR0
BSF
STATUS,RP0
5.4
Prescaler
MOVLW
MOVWF
CLRWDT
b’00101111’
OPTION_REG
;Required if desired
; PS2:PS0 is
; 000 or 001
;
;Set postscaler to
; desired WDT rate
;Bank 0
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this data sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits (OPTION_REG<2:0>).
MOVLW
MOVWF
BCF
b’00101xxx’
OPTION_REG
STATUS,RP0
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
;Clear WDT and
; prescaler
;Bank 1
BSF
STATUS,RP0
b’xxxx0xxx’
MOVLW
;Select TMR0,
; prescale, and
; clock source
;
MOVWF
BCF
OPTION_REG
STATUS,RP0
;Bank 0
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Resets
Value on
POR, BOD
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 Module Register
GIE PEIE T0IE
OPTION_REG GPPU INTEDG T0CS
TRISIO
xxxx xxxx uuuu uuuu
GPIF 0000 0000 0000 0000
PS0 1111 1111 1111 1111
0Bh/8Bh INTCON
INTE
T0SE
GPIE
PSA
T0IF
PS2
INTF
PS1
81h
85h
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: — = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0 module.
DS41211B-page 40
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
