PIC12F683
4.2.4.4
GP3/MCLR/VPP
4.2.4.5
GP4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
Figure 4-5 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
• a general purpose input
• a general purpose I/O
• an analog input for the A/D
• a TMR1 gate input
• as Master Clear Reset with weak pull-up
FIGURE 4-4:
BLOCK DIAGRAM OF GP3
• a crystal/resonator connection
• a clock output
VDD
MCLRE
Weak
FIGURE 4-5:
BLOCK DIAGRAM OF GP4
Data
Bus
Analog
Input Mode
MCLRE
Reset
CLK(1)
Input
pin
Data
Modes
VDD
Bus
RD
TRISIO
VSS
D
Q
Q
MCLRE
VSS
WR
WPU
CK
Weak
RD
GPIO
D
Q
Q
GPPU
RD
WPU
Q
Q
D
Oscillator
Circuit
WR
IOC
CK
OSC1
Q3
EN
VDD
CLKOUT
Enable
RD
IOC
D
Fosc/4
1
0
D
Q
Q
EN
Interrupt-on-
change
I/O pin
WR
GPIO
CK
CLKOUT
Enable
RD GPIO
VSS
D
Q
Q
INTOSC/
RC/EC(2)
WR
TRISIO
CK
CLKOUT
Enable
RD
TRISIO
Analog
Input Mode
RD
GPIO
D
Q
Q
Q
D
D
CK
WR
IOC
EN
Q3
RD
IOC
Q
EN
Interrupt-on-
change
RD GPIO
To T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
DS41211B-page 36
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
