PIC12F683
4.0
GPIO PORT
Note:
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
EXAMPLE 4-1:
INITIALIZING GPIO
BCF
CLRF
STATUS,RP0
GPIO
;Bank 0
;Init GPIO
Note:
Additional information on I/O ports may be
found in the “PICmicro® Mid-Range MCU
Family Reference Manual” (DS33023).
MOVLW 07h
MOVWF CMCON0
;Set GP<2:0> to
;digital I/O
;Bank 1
;digital I/O
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
BSF
CLRF
STATUS,RP0
ANSEL
MOVLW 0Ch
MOVWF TRISIO
4.1
GPIO and the TRISIO Registers
GPIO is
a 6-bit wide, bidirectional port. The
BCF
STATUS,RP0
;Bank 0
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a High-impedance mode). Clearing a TRISIO
bit (= 0) will make the corresponding GPIO pin an
output (i.e., put the contents of the output latch on the
selected pin). The exception is GP3, which is input only
and its TRISIO bit will always read as ‘1’. Example 4-1
shows how to initialize GPIO.
4.2
Additional Pin Functions
Every GPIO pin on the PIC12F683 has an interrupt-on-
change option and a weak pull-up option. GP0 has an
Ultra Low-Power Wake-up option. The next three
sections describe these functions.
4.2.1
WEAK PULL-UPS
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There-
fore, a write to a port implies that the port pins are read,
this value is modified and then written to the port data
latch. GP3 reads ‘0’ when MCLRE = 1.
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 4-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>). A weak pull-up is automatically enabled
for GP3 when configured as MCLR and disabled when
GP3 is an I/O. There is no software control of the MCLR
pull-up.
The TRISIO register controls the direction of the GPIO
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISIO register
are maintained set when using them as analog inputs.
I/O pins configured as analog input always read ‘0’.
REGISTER 4-1:
GPIO – GENERAL PURPOSE I/O REGISTER (ADDRESS: 05h)
U-0
—
U-0
—
R/W-x
GP5
R/W-x
GP4
R/W-x
GP3
R/W-x
GP2
R/W-0
GP1
R/W-0
GP0
bit 7
bit 0
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
GPIO<5:0>: GPIO I/O pin
1= Port pin is > VIH
0= Port pin is < VIL
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2004 Microchip Technology Inc.
Preliminary
DS41211B-page 31
MICROCHIP [ MICROCHIP ]
