PIC12F609/615/12HV609/615
FIGURE 1-2:
PIC12F615/HV615 BLOCK DIAGRAM
INT
Configuration
13
Program Counter
Flash
1K X 14
Program
Memory
Data Bus
8
GPIO
8-Level Stack
(13-Bit)
RAM
64 Bytes
File
Registers
RAM Addr
9
Addr MUX
Program
Bus
GP0
GP1
GP2
GP3
GP4
GP5
14
Instruction Reg
Direct Addr
7
8
Indirect
Addr
FSR Reg
STATUS Reg
8
Power-up
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Internal
Oscillator
Block
MCLR
V
DD
V
SS
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
8
3
MUX
ALU
W Reg
T1G*
T1G
T1CKI
Shunt Regulator
(PIC12HV615 only)
Timer0
T0CKI
Timer1
Timer2
Comparator Voltage Reference
Analog-To-Digital Converter
Absolute Voltage Reference
Analog Comparator
and Reference
ECCP
AN0
AN1
AN2
AN3
CIN+
CIN0-
CIN1-
COUT
CCP1/P1A
P1B
P1A*
P1B*
DS41302A-page 6
V
REF
*
Alternate pin function.
Preliminary
©
2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
