PIC12F609/615/12HV609/615
1.0
DEVICE OVERVIEW
Block Diagrams and pinout descriptions of the devices
are as follows:
• PIC12F609/HV609 (Figure 1-1, Table 1-1)
• PIC12F615/HV615 (Figure 1-2, Table 1-2)
The PIC12F609/615/12HV609/615 devices are covered
by this data sheet. They are available in 8-pin PDIP,
SOIC, TSSOP and DFN packages.
FIGURE 1-1:
PIC12F609/HV609 BLOCK DIAGRAM
INT
Configuration
13
Program Counter
Flash
1K X 14
Program
Memory
Data Bus
8
GPIO
8-Level Stack
(13-Bit)
RAM
64 Bytes
File
Registers
RAM Addr
9
Addr MUX
Program
Bus
GP0
GP1
GP2
GP3
GP4
GP5
14
Instruction Reg
Direct Addr
7
8
Indirect
Addr
FSR Reg
STATUS Reg
8
Power-up
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Internal
Oscillator
Block
T1G
T1CKI
Timer0
T0CKI
Timer1
MCLR
V
DD
V
SS
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
8
3
MUX
ALU
W Reg
Shunt Regulator
(PIC12HV609 only)
Comparator Voltage Reference
Absolute Voltage Reference
Analog Comparator
and Reference
CIN+
CIN0-
CIN1-
COUT
©
2006 Microchip Technology Inc.
Preliminary
DS41302A-page 5
MICROCHIP [ MICROCHIP TECHNOLOGY ]
