MCP7940M
5.0
ON BOARD MEMORY
The MCP7940M has 64 x 8 bytes of on-chip SRAM.
5.1
SRAM
FIGURE 5-1:
SRAM/RTCC BYTE WRITE
S
BUS ACTIVITY
T
S
T
O
P
CONTROL
BYTE
ADDRESS
BYTE
MASTER
A
R
T
DATA
SDA LINE
S 1 1 0 1 1
0
x
1 1
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 5-2:
SRAM/RTCC MULTIPLE BYTE WRITE
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
ADDRESS
BYTE
BUS ACTIVITY
MASTER
DATA BYTE 0
DATA BYTE N
SDA LINE
x
P
1 1 1
S 1 1 0 1
0
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
Note: Entering an address past 5F for an SRAM
operation will result in the MCP7940M not
acknowledging the address.
2012 Microchip Technology Inc.
Preliminary
DS22292A-page 15
MICROCHIP [ MICROCHIP ]
