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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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12.8.2 Timer/Counter Control Register B – TCCR0B  
Bit  
7
FOC0A  
W
6
FOC0B  
W
5
4
3
WGM02  
R/W  
0
2
CS02  
R/W  
0
1
CS01  
R/W  
0
0
CS00  
R/W  
0
TCCR0B  
Read/Write  
Initial Value  
R
0
R
0
0
0
• Bit 7 – FOC0A: Force Output Compare A  
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.  
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating  
in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the waveform  
generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is  
implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced  
compare.  
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.  
The FOC0A bit is always read as zero.  
• Bit 6 – FOC0B: Force Output Compare B  
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.  
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating  
in PWM mode. When writing a logical one to the FOC0B bit, an immediate compare match is forced on the waveform  
generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is  
implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced  
compare.  
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.  
The FOC0B bit is always read as zero.  
• Bits 5:4 – Res: Reserved Bits  
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.  
• Bit 3 – WGM02: Waveform Generation Mode  
See the description in Section 12.8.1 “Timer/Counter Control Register A – TCCR0A” on page 86.  
• Bits 2:0 – CS02:0: Clock Select  
The three clock select bits select the clock source to be used by the Timer/Counter.  
Table 12-9. Clock Select Bit Description  
CS02  
CS01  
CS00  
Description  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (Timer/Counter stopped)  
clkI/O/(no prescaling)  
clkI/O/8 (from prescaler)  
clkI/O/64 (from prescaler)  
clkI/O/256 (from prescaler)  
clkI/O/1024 (from prescaler)  
External clock source on T0 pin. Clock on falling edge.  
External clock source on T0 pin. Clock on rising edge.  
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is  
configured as an output. This feature allows software control of the counting.  
ATmega16/32/64/M1/C1 [DATASHEET]  
89  
7647O–AVR–01/15  
 
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