Write Status Register (WRSR):
The WRSR instruction allows the user to select one of four levels of protection.
The AT25128B/256B is divided into four array segments. None, one-quarter (
¼)
, one-half (
�½)
, or all of the
memory segments can be protected. Any of the data within any selected segment will therefore be read-only.
The block write protection levels and corresponding status register control bits are shown in
Bits BP1, BP0, and WPEN are nonvolatile cells that have the same properties and functions as the regular
memory cells (e.g., WREN, t
WC
, RDSR).
Table 6-4.
Block Write Protect Bits
Status Register Bits
Level
0
1 (
¼
)
2 (
�½
)
3 (All)
BP1
0
0
1
1
BP0
0
1
0
1
Array Addresses Protected
AT25128B
None
3000 – 3FFF
2000 – 3FFF
0000 – 3FFF
AT25256B
None
6000 – 7FFF
4000 – 7FFF
0000 – 7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN
bit is one. The hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero.
When the device is hardware write protected, writes to the Status Register including the Block Protect bits, the
WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to
sections of the memory which are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP
pin is held low.
WPEN Operation
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
Table 6-5.
WPEN
0
0
1
1
X
X
Read Sequence (READ):
Reading the AT25128B/256B via the SO pin requires the following sequence. After
the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the byte
address to be read (
). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The Read Sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll-over to the lowest address allowing the entire memory to be read in one continuous
read
cycle.
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
