6.
Functional Description
The AT25128B/256B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of
the 6800 series of microcontrollers.
The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are
contained in
All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low CS transition.
Table 6-1.
Instruction Set for the AT25010B/020B/040B
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Write Enable (WREN):
The device will power-up in the Write Disable state when V
CC
is applied. All
programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held
high during a WREN instruction.
Write Disable (WRDI):
To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
Read Status Register (RDSR):
The Read Status Register instruction provides access to the status register.
The Read/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6-2.
Bit 7
WPEN
Status Register Format
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 6-3.
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Read Status Register Bit Definition
Definition
Bit 0 = 0 (RDY) indicates the device is ready.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1 = 0 indicates the device
is not
write enabled.
Bit 1 = 1 indicates the device is write enabled.
See
See
See
Bits 4 to 6 are zeros when the device is not in an internal write cycle.
Bit 7 (WPEN)
Bits 0 to 7 are ones during an internal write cycle.
8
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
MICROCHIP [ MICROCHIP TECHNOLOGY ]
