Figure 7-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
Data Out
High-impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 7-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
5
11
12
13
14
1
15
0
SCK
SI
Data In
3
Instruction
7
6
4
2
High-impedance
SO
Figure 7-6.
READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
Byte Address
...
Instruction
AN
A0
Data Out
High-impedance
SO
7
6
5
4
3
2
1
0
MSB
12
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015