Table 4-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
25
50
100
tLZ
Hold to Output Low Z
ns
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
25
50
100
tHZ
Hold to Output High Z
Output Disable Time
ns
ns
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
25
50
100
tDIS
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
3.3V, 25C, Page Mode
1,000,000
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
5.
Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave.
Transmitter/Receiver: The AT25128B/256B has separate pins designated for data transmission (SO) and
reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode which defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25128B/256B, and the serial
output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
Chip Select: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the SO pin will remain in a high-impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high-impedance
state.
Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is
blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25128B/256B
in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions
are enabled when the WPEN bit is set to one.
6
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
MICROCHIP [ MICROCHIP ]
