PIC12CE67X
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
36
RESET
34
31
34
I/O Pins
TABLE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
7
—
—
µs VDD = 5V, –40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
18
33
ms VDD = 5V, –40˚C to +125˚C
(No Prescaler)
32
33*
34
Tost
Oscillation Start-up Timer Period
—
28
—
1024TOSC
—
132
2.1
—
TOSC = OSC1 period
Tpwrt Power up Timer Period
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
These parameters are characterized but not tested.
72
—
ms VDD = 5V, –40˚C to +125˚C
TIOZ
µs
*
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 93
MICROCHIP [ MICROCHIP ]
