PIC12CE67X
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
4.1
Program Memory Organization
The PIC12CE67X has a 13-bit program counter capa-
ble of addressing an 8K x 14 program memory space.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
For the PIC12CE673 the first 1K x 14 (0000h-03FFh) is
implemented.
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
For the PIC12CE674, the first 2K x 14 (0000h-07FFh)
is implemented. Accessing a location above the physi-
cally implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC12CE67X PROGRAM
MEMORY MAP AND STACK
Also note that F0h through FFh on the PIC12CE67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
0400h
(PIC12CE674 only)
07FFh
0800h
1FFFh
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 11
MICROCHIP [ MICROCHIP ]
