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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED)  
Address  
Name  
FORWARD Port Map  
[4:0] Each bit indicates forwarding decision of one port.  
Description  
Mode  
Default  
4 - 0  
R/W  
Bit[0] = Port 1  
Bit[1] = Port 2  
Bit[2] = Port 3  
Bit[3] = Port 4  
Bit[4] = Port 5  
When MD = 01 and ENB = 00,  
Bit[4] is used as count unit:  
0 = µs  
1 = ms  
Bit[3] is used to select count modes:  
0 = count down in the 11-bit counter from an  
assigned value in the Action field PM, P, RPE, RP,  
and MM, an interrupt will be generated when  
expired.  
1 = count up in the 11-bit counter for every matched  
packet received up to reach an assigned value in  
the Action field PM, P, RPE, RP and MM, and then  
an interrupt will be generated.  
Note: See ENB field description for detail.  
Port_ACL_C  
ACL Port Register 12 (0x0C)  
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.  
Reg. 111 (0x6F) Bits[7:0] = Offset 0x0C to access the Indirect Byte Register 0xA0.  
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.  
Processing Field  
7 - 0  
RULESET Rule Set  
[15:8] Each bit indicates this entry in bits 0 to 16, total 16  
R/W  
00000000  
entries of the rule list can be assigned for the rule  
set to be used in the rules cascade per port.  
Port_ACL_D  
ACL Port Register 13 (0x0D)  
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.  
Reg. 111 (0x6F) Bits[7:0] = Offset 0x0D to access the Indirect Byte Register 0xA0.  
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.  
Processing Field  
7 - 0  
RULESET Rule Set  
[7:0] Each bit indicates this entry in bits 0 to 16, total 16  
R/W  
00000000  
entries of the rule list can be assigned for the rule  
set to be used in the rules cascade per port.  
TABLE 4-22: TEMPORAL STORAGE FOR 14 BYTES ACL RULES  
Address Name Description  
Mode  
Default  
Port_ACL_BYTE_ENB_MSB  
ACL Port Register 14 (0x10)  
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, and 4.  
Reg. 111 (0x6F) Bits[7:0] = Offset 0x10 to access the Indirect Byte Register 0xA0.  
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.  
7 - 6  
Reserved  
RO  
00  
DS00002112A-page 94  
2016 Microchip Technology Inc.  
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