KSZ8795CLX
TABLE 4-24: EEE GLOBAL REGISTERS (CONTINUED)
Address
Name
Description
Mode
Default
7
LPI
1 = LPI request will be stopped if input traffic is
R/W
0
Terminated detected.
By Input Traf- 0 = LPI request won’t be stopped by input traffic.
fic Enable
6 - 0
Reserved
—
RO
0x10
0x10
EEE Global Register 1
Global Empty TXQ to LPI Wait Time Control Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x32 (Bits[15:8]), 0x33 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 0
Empty TXQ This register specifies the time that the LPI request
to LPI Wait will be generated after a TXQ has been empty
R/W
Time
exceeds this configured time. This is only valid
when EEE 100BT is enabled. This setting will apply
to all the ports. The unit is 1.3 ms. The default
value is 1.3s (range from 1.3 ms to 86 seconds)
EEE Global Register 2
Global EEE PCS DIAGNOSTIC Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x34(Bits[15:8]), 0x35 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 12
11 - 8
7 - 4
3
Reserved
Reserved
Reserved
—
—
—
RO
RO
0x6
0x8
0x0
1
RO
Port 4 Next 1 = Enable next page exchange during Auto-Nego-
R/W
Page Enable tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
2
1
0
Port 3 Next 1 = Enable next page exchange during Auto-Nego-
Page Enable tiation.
R/W
R/W
R/W
1
1
1
0 = Skip next page exchange during Auto-Negotia-
tion.
Port 2 Next 1 = Enable next page exchange during Auto-Nego-
Page Enable tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
Port 1 Next 1 = Enable next page exchange during Auto-Nego-
Page Enable tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
EEE Global Register 3
Global EEE Minimum LPI cycles before back to Idle Control Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x36 (Bits[15:8], 0x37 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 0
Reserved
—
RO
0x0000
DS00002112A-page 98
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
