KSZ8795CLX
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED)
Address
Name
Description
Mode
Default
2 - 1
PC[1:0]
00 = The port comparison is disabled.
01 = Matching either one of MAX or MIN.
10 = Match if the port number is in the range of
MAX and MIN.
R/W
00
11 = Match if the port number is out of the range
0
PRO[7]
IP Protocol
—
0
For the IP protocol to be matched
Port_ACL_5
ACL Port Register 5 (0x05)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x05 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 4
7 - 1
PRO[6:0]
IP Protocol
For the IP protocol to be matched
R/W
0000000
0
0
FME
Flag Match Enable
R/W
0 = Disable TCP FLAG matching
1 = Enable TCP FLAG matching
Port_ACL_6
ACL Port Register 6 (0x06)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x06 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 4
7 - 0
FMSK[7:0] TCP FLAG Mask
R/W
00000000
Port_ACL_7
ACL Port Register 7 (0x07)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 4
7 - 0
FLAG[7:0] TCP FLAG
R/W
00000000
00000000
00000000
Port_ACL_8
ACL Port Register 8 (0x08)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x08 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
7 - 0
Reserved
—
RO
Port_ACL_9
ACL Port Register 9 (0x09)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
7 - 0
Reserved
—
RO
Note: Layer 2, Layer 3, and Layer 4 in matching field should be in different entries. Same layer should be in same
entry.
DS00002112A-page 92
2016 Microchip Technology Inc.
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