KSZ8795CLX
Write 0x00 to Register 111 (0x6F) // trigger the read/burst read operation(s) based on the Byte Enable Register set-
ting by the Port 1 ACL access Register 0 (0x00). Read/Burst read the Indirect Byte Register 160 (0xA0) // to get data of
ACL entry word 0, write 0x00 to 0x0D indirect address and read Register 160 (0xA0) after each byte address write to
Register 111 (0x6F).
Write Operation
1. Steps set Byte Enable register to select odd address bytes in ACL word:
Use the Indirect Access Control Register to select register to be written. To write even byte number of 15th entry of Port
5:
Write 0x55 to Register 110 (0x6E) // select ACL and read to Port 5.
Write 0x12 to Register 111 (0x6F) // trigger the read operation for Port 5 ACL Access Control Register read.
Read the Indirect Byte Register 160 (0xA0) to get data (If Bit[6] is set, the previous write completes and go to next
step. Otherwise, repeat the above polling step).
Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 5.
Write 0x00 to Register 111 (0x6F) //set offset address for Port 5 ACL Port Register 0.
Write/Burst write the Indirect Byte Register 160 (0xA0) for ACL Port Register 0, 1, 2, …,13 from 0x00 to 0x0D)
(Write or Burst write even bytes of Port 5 ACL access Registers 0, 1, …, 13 to holding buffer).
Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 5.
Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 5 in the ACL Port Register 14 (Byte Enable
MSB register).
Write 0x15 into the Indirect Byte Register 160 (0xA0) for MSB of Byte Enable word to enable odd bytes address
0x01, 0x03 and 0x05.
2. Steps set ACL Control Register to write ACL entry word 15 from holding buffer:
Write 0x45 to Register 110 (0x6E) // select write to Port 5.
Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 5 in the ACL Port Register 15 (Byte Enable
LSB register).
Write 0x55 into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word to enable odd bytes address
0x07, 0x09, 0x0B and 0x0D.
Write 0x45 to Register 110 (0x6E) // select write to Port 5.
Write 0x12 to Register 111 (0x6F) // write the port ACL access control register address (0x12) to the Indirect
Address Register 111 for setting the write operation to Port 5 in the ACL Port Register 16 to write entry 15 bytes 1, 3,
5…,13.
Write 0x1F into the Indirect Byte Register 160 (0xA0) // for the write operation to 15th entry in the ACL Port Register
16 (0x12) bit4=1 to write ACL, Bits[3:0] = 0xF to write entry 15.
The bit arrangement of the example above assumes Layer 2 rule of MODE = 01 in ACL Port Register 1 (0x01), refer to
ACL format for MODE = 10 and 11.
4.9
EEE Indirect Registers
The EEE function is for all copper ports only. The EEE registers are provided on global and per-port basis. These reg-
isters are read/write using indirect memory access as below: LPI means low power idle.
TABLE 4-24: EEE GLOBAL REGISTERS
Address
EEE Global Register 0
Global EEE QM Buffer Control Register
Name
Description
Mode
Default
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x30 (Bits[15:8]), 0x31 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 8
Reserved
—
RO
0x40
2016 Microchip Technology Inc.
DS00002112A-page 97
MICREL [ MICREL SEMICONDUCTOR ]
