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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED)  
Address  
Name  
Description  
Mode  
Default  
6 - 0  
Port Queue 2 Egress Data Rate Limit For Priority 2 Frames  
Egress Limit Egress traffic from this port is shaped according to  
the Table 18 in “Rate Limiting Support” sub-section.  
In four queues mode, it is high/low priority.  
R/W  
0000000  
Register 190 (0xBE): Port 1 Queue 3 Egress Limit Control 4  
Register 206 (0xCE): Port 2 Queue 3 Egress Limit Control 4  
Register 222 (0xDE): Port 3 Queue 3 Egress Limit Control 4  
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4  
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4  
7
Reserved  
RO  
0
6 - 0  
Port Queue 3 Egress Data Rate Limit For Priority 3 Frames  
Egress Limit Egress traffic from this port is shaped according to  
the Table 18 in “Rate Limiting Support” sub-section.  
In four queues mode, it is highest priority.  
R/W  
0000000  
Note 4-1  
In the port priority 0 - 3 ingress rate limit mode, it is necessary to set all related egress ports to two  
queues or four queues mode.  
In the port queue 0 - 3 egress rate limit mode, the highest priority get exact rate limit based on the  
rate select table, other priorities packets rate are based upon the ratio of the Port Control 14/15/16/  
17 Registers when using more than one egress queue per port.  
TABLE 4-14: ADVANCED CONTROL REGISTERS 191 - 255  
Address Name Description  
Register 191 (0xBF): Testing Register  
7 - 0 Reserved N/A Don’t Change.  
Register 207 (0xCF): Reserved Control Register  
7 - 0 Reserved N/A Don’t Change.  
Register 223 (0xDF): Test Register 2  
7 - 0 Reserved N/A Don’t Change.  
Register 239 (0xEF): Test Register 3  
7 - 0 Reserved N/A Don’t Change.  
Register 255 (0xFF): Testing Register 4  
7 - 0 Reserved N/A Don’t Change.  
Mode  
Default  
RO  
RO  
RO  
RO  
RO  
0x80  
0x15  
0x0C  
0x32  
0x00  
TABLE 4-15: INDIRECT REGISTER DESCRIPTIONS  
Control  
Indirect Address  
Contents  
Direct Address 0x6E,  
Function Select Bits[7-5] = 000,  
Table_select Bits[3-2] = 00  
0x000 – 0x01F  
0x000 – 0x1FF  
0x000 – 0x1FF  
Static MAC address table entry 0 – 31  
Direct Address 0x6E,  
Function Select Bits[7-5] = 000,  
Table_select Bits[3-2] = 01  
VLAN table bucket 0 – 1023 (4 entries  
per bucket)  
Direct Address 0x6E,  
Function Select Bits[7-5] = 000,  
Table_select Bits[3-2] = 10  
Dynamic MAC address table entry 0 –  
1023  
DS00002112A-page 78  
2016 Microchip Technology Inc.  
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