KSZ8795CLX
TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED)
Address
Name
Port-Based Ingress Data Rate Limit For Priority 2 Frames
Priority 2 Ingress traffic from this port is shaped according to
Ingress Limit the Table 18 in “Rate Limiting Support” sub-section.
Description
Mode
Default
6 - 0
R/W
0000000
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4
7
Port-Based Ingress Data Rate Limit For Priorities Setting Valid
Ingress Rate Trigger port ingress rate limit engine to take effect
Limit Enable for all the priority queues according to priority
ingress limit control.
R/W
0
Note: Any write to this register will trigger port
ingress rate limit engine to take effect for all the pri-
ority queues according to priority ingress limit con-
trol. For the port priority 0 - 3 ingress rate limit
control to take effect, Bit[7] of in Register 186, 202,
218, 234 and 250 for Ports 1, 2, 3, 4 and 5, respec-
tively will need to set last after configured Bits[6:0]
of Port Ingress Limit Control 1 - 4 registers.
6 - 0
Port-Based Ingress Data Rate Limit For Priority 3 Frames
R/W
0000000
Priority 3
Ingress traffic from this port is shaped according to
Ingress Limit the Table 18 in “Rate Limiting Support” sub-section.
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1
7
Reserved
—
RO
0
6 - 0
Port Queue 0 Egress Data Rate Limit For Priority 0 Frames
Egress Limit Egress traffic from this port is shaped according to
the Table 18 in “Rate Limiting Support” sub-section.
In four queues mode, it is lowest priority.
R/W
0000000
In two queues mode, it is low priority.
Register 188 (0xBC): Port 1 Queue 1 Egress Limit Control 2
Register 204 (0xCC): Port 2 Queue 1 Egress Limit Control 2
Register 220 (0xDC): Port 3 Queue 1 Egress Limit Control 2
Register 236 (0xEC): Port 4 Queue 1 Egress Limit Control 2
Register 252 (0xFC): Port 5 Queue 1 Egress Limit Control 2
7
Reserved
—
RO
0
6 - 0
Port Queue 1 Egress Data Rate Limit For Priority 1 Frames
Egress Limit Egress traffic from this port is shaped according to
the Table 18 in “Rate Limiting Support” sub-section.
In four queues mode, it is low/high priority.
R/W
0000000
In two queues mode, it is high priority.
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3
7
Reserved
—
RO
0
2016 Microchip Technology Inc.
DS00002112A-page 77
MICREL [ MICREL SEMICONDUCTOR ]
