KSZ8795CLX
TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED)
Address
Name
Description
Mode
Default
0
InsertSource Register 176: Insert source Port 1 PVID for
Port PVID for untagged frame at egress Port 2
R/W
0
Untagged
Register 192: Insert source Port 2 PVID for
Packet Desti- untagged frame at egress Port 1
nation to
Lowest
Register 208: Insert source Port 3 PVID for
untagged frame at egress Port 1
Egress Port Register 224: Insert source Port 4 PVID for
untagged frame at egress Port 1
Register 240: Insert source Port 5 PVID for
untagged frame at egress Port 1
Note: Enabled by the Register 135 Bit[2].
Register 177 (0xB1): Port 1 Control 13
Register 193 (0xC1): Port 2 Control 13
Register 209 (0xD1): Port 3 Control 13
Register 225 (0xE1): Port 4 Control 13
Register 241 (0xF1): Port 5 Control 13
7 - 2
1
Reserved
—
RO
000000
0
4 Queue Split This bit, in combination with Register16/32/48/64/
R/W
Enable
80 Bit[0], will select the split of 1, 2, and 4 queues:
{Register 177 Bit[1], Register 16 Bit[0] = }:
11 = Reserved.
10 = The port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
01 = The port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
00 = Single output queue on the port. There is no
priority differentiation even though packets are
classified into high and low priority.
0
Enable Drop- 0 = Disable tagged packets drop
ping Tag 1 = Enable tagged packets drop
R/W
0
Register 178 (0xB2): Port 1 Control 14
Register 194 (0xC2): Port 2 Control 14
Register 210 (0xD2): Port 3 Control 14
Register 226 (0xE2): Port 4 Control 14
Register 242 (0xF2): Port 5 Control 14
7
Enable Port 0 = Strict priority, will transmit all the packets from
R/W
R/W
1
Transmit
Queue 3
Ratio
this priority queue 3 before transmit lower priority
queue.
1 = Bits[6:0] reflect the packet number allow to
transmit from this priority queue 3 within a certain
time.
6 - 0
Port Trans- Packet number for Transmit Queue 3 for highest
mit Queue 3 priority packets in four queues mode.
Ratio[6:0]
0001000
DS00002112A-page 74
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
