KSZ8795CLX
TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED)
Address
Name
Description
Mode
Default
5
Ingress Limit 1 = Rate limit is counted based on number of
Bit/Packets packet.
R/W
0
Mode Select 0 = Rate limit is counted based on number of bit.
4
Ingress Rate 1 = Flow Control is asserted if the port’s receive
Limit Flow rate is exceeded.
R/W
R/W
0
Control
Enable
0 = Flow Control is not asserted if the port’s receive
rate is exceeded.
3 - 2
Limit Mode Ingress Limit Mode
These bits determine what type of frames are lim-
00
ited and counted against ingress rate limiting.
00 = Limit and count all frames.
01 = Limit and count Broadcast, Multicast, and
flooded unicast frames.
10 = Limit and count Broadcast and Multicast
frames only.
11 = Limit and count Broadcast frames only.
1
0
Count IFG Count IFG Bytes
R/W
R/W
0
0
1 = Each frame’s minimum inter-frame gap. (IFG)
bytes (12 per frame) are included in Ingress and
Egress rate limiting calculations.
0 = IFG bytes are not counted.
Count Pre Count Preamble Bytes
1 = Each frame’s preamble bytes (8 per frame) are
included in Ingress and Egress rate limiting calcu-
lations.
0 = Preamble bytes are not counted.
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
7
Reserved
Port Based Ingress Data Rate Limit For Priority 0 Frames
Priority 0 Ingress traffic from this port is shaped according to
Ingress Limit the Table 18 in “Rate Limiting Support” sub-section.
—
RO
0
6 - 0
R/W
0000000
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
7
Reserved
Port-Based Ingress Data Rate Limit For Priority 1 Frames
Priority 1 Ingress traffic from this port is shaped according to
Ingress Limit the Table 18 in “Rate Limiting Support” sub-section.
—
RO
0
6 - 0
R/W
0000000
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
7
Reserved
—
RO
0
DS00002112A-page 76
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
