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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1)  
Address  
Name  
Description  
Mode  
Default  
Register 176 (0xB0): Port 1 Control 12  
Register 192 (0xC0): Port 2 Control 12  
Register 208 (0xD0): Port 3 Control 12  
Register 224 (0xE0): Port 4 Control 12  
Register 240 (0xF0): Port 5 Control 12  
7
6
Reserved  
RO  
1
0
Pass All  
Frames  
Port-based enable to pass all frames  
1 = Enable  
R/W  
0 = Disable  
Note: This is used in the port mirroring with RX  
sniff only.  
5 -4  
3
Reserved  
RO  
00  
0
InsertSource Register 176: Insert source Port 1 PVID for  
Port PVID for untagged frame at egress Port 5  
R/W  
Untagged  
Register 192: Insert source Port 2 PVID for  
Packet Desti- untagged frame at egress Port 5  
nation to  
Highest  
Register 208: Insert source Port 3 PVID for  
untagged frame at egress Port 5  
Egress Port Register 224: Insert source Port 4 PVID for  
untagged frame at egress Port 5  
Register 240: Insert source Port 5 PVID for  
untagged frame at egress Port 4  
Note: Enabled by the Register 135 Bit[2].  
2
InsertSource Register 176: Insert source Port 1 PVID for  
Port PVID for untagged frame at egress Port 4  
R/W  
0
Untagged  
Register 192: Insert source Port 2 PVID for  
Packet Desti- untagged frame at egress Port 4  
nation to  
Second  
Highest  
Register 208: Insert source Port 3 PVID for  
untagged frame at egress Port 4  
Register 224: Insert source Port 4 PVID for  
Egress Port untagged frame at egress Port 3  
Register 240: Insert source Port 5 PVID for  
untagged frame at egress Port 3  
Note: Enabled by the Register 135 Bit[2].  
1
InsertSource Register 176: Insert source Port 1 PVID for  
Port PVID for untagged frame at egress Port 3  
R/W  
0
Untagged  
Packet Desti- untagged frame at egress Port 3  
nation to Register 208: Insert source Port 3 PVID for  
Register 192: Insert source Port 2 PVID for  
Second Low- untagged frame at egress Port 2  
est Egress Register 224: Insert source Port 4 PVID for  
Port  
untagged frame at egress Port 2  
Register 240: Insert source Port 5 PVID for  
untagged frame at egress Port 2  
Note: Enabled by the Register 135 Bit[2].  
2016 Microchip Technology Inc.  
DS00002112A-page 73  
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