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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
TABLE 4-4:  
Address  
1 0  
PORT REGISTERS (CONTINUED)  
Name  
Description  
Mode  
Default  
Interface Mode Select  
These bits select the interface type and mode for  
Switch Port 5 (SW5).  
R/W  
11  
Note: This is for port 5 Port 5 Mode Select:  
SW5-GMII/RGMII/MII/ 00 = MII  
RMII  
01 = RMII  
10 = GMII  
11 = RGMII.  
Strap-in option: LED3[1:0]  
00 = MII  
01 = RMII  
10 = GMII  
11 = RGMII (Default)  
Note: These pins have internal pull-ups.  
Register 23 (0x17): Port 1 Control 7 (Note 4-1)  
Register 39 (0x27): Port 2 Control 7  
Register 55 (0x37): Port 3 Control 7  
Register 71 (0x47): Port 4 Control 7  
Register 87 (0x57): Reserved  
7 6  
5 4  
Reserved  
N/A Don’t Change.  
RO  
00  
11  
Advertised_Flow_Con- These bits indicate that the KSZ8795CLX has  
R/W  
trol _Capability  
implemented both the optional MAC control sub-  
layer and the PAUSE function as specified in IEEE  
Clause 31 and Annex 31B for full duplex operation  
independent of rate and medium.  
00 = No pause  
01 = Symmetric PAUSE  
10 = Asymmetric PAUSE toward link partner  
toward link partner  
11 = Both Symmetric PAUSE and Asymmetric  
PAUSE toward local devices  
Bit[5] indicates that asymmetric PAUSE is sup-  
ported. The value of Bit[4] when Bit[5] is set indi-  
cates the direction of the PAUSE frames that are  
supported for flow across the link. Asymmetric  
PAUSE configuration results in independent  
enabling of the PAUSE receive and PAUSE trans-  
mit functions as defined by IEEE Annex 31B.  
3
2
1
0
Advertised 100BT Full- 1 = Advertise 100BT full-duplex capability.  
R/W  
R/W  
R/W  
R/W  
1
1
1
1
Duplex Capability  
0 = Suppress 100BT full-duplex capability from  
transmission to link partner.  
Advertised 100BT Half- 1 = Advertise 100BT half-duplex capability.  
Duplex Capability  
0 = Suppress 100BT half-duplex capability from  
transmission to link partner.  
Advertised 10BT Full- 1 = Advertise 10BT full-duplex capability.  
Duplex Capability  
0 = Suppress 10BT full-duplex capability from  
transmission to link partner.  
Advertised 10BT Half- 1 = Advertise 10BT half-duplex capability.  
Duplex Capability  
0 = Suppress 10BT half-duplex capability from  
transmission to link partner.  
DS00002112A-page 58  
2016 Microchip Technology Inc.  
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