KSZ8795CLX
TABLE 4-4:
Address
PORT REGISTERS (CONTINUED)
Name
Description
Mode
Default
Register 30 (0x1E): Port 1 Status 2
Register 46 (0x2E): Port 2 Status 2
Register 62 (0x3E): Port 3 Status 2
Register 78 (0x4E): Port 4 Status 2
Register 94 (0x5E): Reserved
(Note 4-1)
7
MDIX Status
1 = MDI.
0 = MDI-X.
RO
RO
RO
RO
0
6
Auto-Negotiation Done 1 = Auto-Negotiation done.
0 = Auto-Negotiation not done.
0
0
5
Link Good
1 = Link good.
0 = Link not good.
4 0
Reserved
N/A Don’t Change.
00000
Register 31 (0x1F): Port 1 Control 11 and Status 3
Register 47 (0x2F): Port 2 Control 11 and Status 3
Register 63 (0x3F): Port 3 Control 11 and Status 3
Register 79 (0x4F): Port 4 Control 11 and Status 3
Register 95 (0x5F): Reserved
(Note 4-1)
7
PHY Loopback
1 = Perform PHY loopback. Loop back path is as
follows:
R/W
0
Example
Set Port 1 PHY Loopback (Reg. 31, Bit[7] = (‘1’)
Use the Port 2 as monitor port. The packets will
transfer.
Start: Port 2 receiving (also can start from Port 3, 4,
5).
Loopback: PMD/PMA of Port 1’s PHY
End: Port 2 transmitting (also can end at Ports 3, 4,
5 respectively).
Setting Reg. 47, 63, 79, 95, Bit[7] = ‘1’ will perform
PHY loopback on Port 2, 3, 4, 5 respectively.
0 = Normal Operation.
6
5
Reserved
N/A Don’t Change
RO
0
0
PHY Isolate
1 = Electrical isolation of PHY from the internal MII
and TX+/TX.
R/W
0 = Normal operation.
4
3
Soft Reset
Force Link
1 = PHY soft reset. This bit is self-clearing.
0 = Normal operation.
R/W
(SC)
0
0
1 = Force link in the PHY.
0 = Normal operation
R/W
2 0
Port Operation Mode
Indication
Indicate the current state of port operation mode:
000 = Reserved
RO
001
001 = Still in Auto-Negotiation
010 = 10BASE-T half duplex
011 = 100BASE-TX half duplex
100 = Reserved
101 = 10BASE-T full duplex
110 = 100BASE-TX full duplex
111 = Reserved
Note 4-1
Port Control 7 - 11 and Port Status 1 - 3 contents can be accessed by the MDC/MDIO interface via
the standard MIIM Registers.
DS00002112A-page 62
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
